The present invention relates to a circuit for supplying an operational voltage in a memory device. More particularly, the present invention relates to a circuit for supplying an operational voltage in a memory device that prevents an unnecessary consumption of current. The circuit changes a dead zone in accordance with an operational mode when supplying a precharge voltage for a bit line of a dynamic random access memory (hereinafter, referred to as “DRAM”), or for a cell plate voltage.
The amount of data to be processed by computers has increased. Accordingly, a speedup in the processing of data is required.
For example, the storage capacity of DRAM devices has improved by leaps and bounds in accordance with the development of miniature forming technique over a memory cell pattern. Accordingly, a storage device made up of one chip can store more data quantity.
Generally, the DRAM memorizes information as a charge in a metal oxide semiconductor capacitor (hereinafter, referred to as “MOS capacitor”). Based upon the charging or discharging of one MOS capacitor, it is determined whether data information for a bit is memorized. That is, the charging condition corresponds to ‘high’, and the discharging condition corresponds to ‘low’. As a result, the condition of memorized information may be determined by one capacitor for one bit.
On the other hand, to maintain the record of data in the DRAM, an operation of again writing the data should be performed so that the charge is not discharged by comparing the voltage with a reference voltage. This re-writing operation is referred to as refresh.
In case the DRAM is a MOS integrated circuit, when the condition of the integrated circuit is bad, charge in the DRAM device is discharged by a leakage current in a few milliseconds (ms), and thus the DRAM should generally be recharged in 2 ms. Accordingly, the DRAM device refreshes every memory cell therein in less than 2 ms.